The present invention relates to a semiconductor memory circuit, and more specially to an electrically erasable and programmable read only memory (hereinafter referred to as "EEPROM circuit").
Conventional technologies on EEPROM circuits are disclosed in U.S. Pat. No. 4,901,320 (hereinafter called "reference No. 1") and Japanese Patent Laid-Open Publication No. 64-59693 (hereinafter called "reference No. 2"). The reference No. 1 concerns a principle and a procedure for error correction for an EEPROM. The reference No. 2 concerns an EEPROM operable with use of low voltage and low current.
Recently, there has been an increasing demand for a highly reliable EEPROM circuit. That is, an EEPROM circuit which is operable with use of low voltage and low current, serviceable for a relatively longer period of life time, high in reliability, and capable of detecting faults, has been demanded.